Beskjeder

Deadline for approval of lab exercises is 23:59 today 3 December.

Har lagt ut en meget enkel simulerings model av MCP3204 ADC i forbindelse med VHDL lab3 (se under laboppgaver). Den kan inkulderes i testbenken som en component og kobles opp mot kontrollermodulen som dere skal lage.

RT-lab no.2 text and source code can now be downloaded.

Lecture plan updated 20 Sep on the FYS4220 web.

Text book for the programmable logic part: "Digital System Design with VHDL", Second Edition, by Mark Zwolinsky. More copies have been ordered by the book store, will arrive in 2 weeks or less.

Register for the course before 10 September in order to be assigned to a lab group. The lab exercises are obligatory.

Lectures and lab exercises in Programmable logic from 2011 are now on FYS4220 web. Note that they may be modified.

Email Skaali: t.b.skaali@fys.uio.no - phone 9520 9239. Email Chengxin: chengxin.zhao@fys.uio.no