Lab-2

Lab. assignment number 2 is now available: /studier/emner/matnat/fys/FYS4220/h13/labs/lab2.pdf.

Lab 2. can be performed without the use of the DE2-70 board as it only involves VHDL design and simulation. The design in lab 2. will later be tested on hardware during lab. 3. 

During week 39 both Ketil and Chengxin will be absent due to travelling (conference). This unfortunately means that there will be no support during the lab. sessions. To compensate for this the due date for lab 2. has been postponed to 11/10.