(Version for Spring 2021. If you access this later, the information might be outdated! See here for the version for 2022!)
In this course's lab tasks you’ll use a professional ASIC layout tool to conduct simulations of circuits with a high level of detail, much more detail than the simple models used in the course book. The program runs under Linux and it will be set up to simulate circuits implemented in a 65nm CMOS technology.
Important: please always close Cadence if you are not using it and before logging out! We do have only a limited number of licences and if you leave Cadence running the licence might not be returned to the licence server correctly for someone else to use.