Changes to requirements for Exercise 3

Given the requirements for the Cadence design exercise, you will end up with very high open loop gain of the operational amplifier. We assume you will not be able to meet this gain requirement and therefore ask you to make it as high as you practically can using standard topologies found in text-books and reasonable efforts. In addition we ask you to explain how the limited gain will affect the performance of the SC Integrator.

Please also note that you can still re-use your op-amp design in the course project as the gain requirements in the  ADC circuit will be more relaxed.