INF5430 - Spring 2015

Teaching plan

Date	Teacher	Place	Topic	Lecture notes / comments
20.01.2015	Roar Skogstr?m	Postscript	INF5430 course presentation. Digital Arithmetic HW Design 1	Israel Koren: Computer Arithmetic Algorithms. Lecture slides
21.01.2015	Roar Skogstr?m	Logo	SystemVerilog 1	Introduction to SystemVerilog. Lecture slides
27.01.2015	Roar Skogstr?m	Postscript	Digital Arithmetic HW Design 2 and lab1 presentation.	Israel Koren: Computer Arithmetic Algorithms. Lecture slides. lab1 with submission deadline February 23'th 2015 is here. Write-Only-Memory (WOM) datasheet (joke!!).
28.01.2015	Roar Skogstr?m	Perl	SystemVerilog 2	SystemVerilog for Verification chapter 1 and start with chapter 2. Lecture slides are here and videos are here.
03.02.2015	Roar Skogstr?m	Postscript	Digital Arithmetic HW Design 3	Israel Koren: Computer Arithmetic Algorithms. Lecture slides
04.02.2015	Roar Skogstr?m	Perl	SystemVerilog 3	SystemVerilog for Verification continue with chapter 2 and chapter 3. Videos are here.
10.02.2015	Roar Skogstr?m	Postscript	Digital Arithmetic HW Design 4	Integer division arithmetic. Lecture slides
11.02.2015	J?rgen Norendal	Perl	Digital HW design 1.	Sequential circuit design and Register Transfer Methodology: Principle P.P. Chu chapter 9.1-3 and 9.5. Slides and Videos
17.02.2015	J?rgen Norendal	Postscript	Digital HW design 2.	Register Transfer Methodology: Principle P.P.Chu chapter 11 and 12.1-5. Slides and Videos
18.02.2015	Roar Skogstr?m	Perl	SystemVerilog 4	SystemVerilog for Verification Chapter 4 and 5 (video selfstudy!!). Lecture slides are here and chapter 5 video is here. Complete solutions to all end of chapter exercises in the book are here . Some SystemVerilog questions and answers are here . SystemVerilog for design reference books are here (NOT part of the curriculum).
24.02.2015	J?rgen Norendal	Postscript	Digital HW design 3. Lab2 presentation.	Clock and synchronization. P.P.Chu chapter 16.5-11. Slides and Videos. lab2 with submission deadline March 23'th 2015 is here.
25.02.2015	Roar Skogstr?m	Perl	SystemVerilog 5.	SystemVerilog for Verification chapter 7. Lecture slides are here.
03.03.2015	J?rgen Norendal	Postscript	Low Power HW Design 1	Jan Rabaey: Low Power Design Essentials chapter 1, 3, 4 and 5 Slides.
04.03.2015				AVLYST
10.03.2015	J?rgen Norendal	Postscript	Low Power HW Design 2	Jan Rabaey: Low Power Design Essentials chapter 6, 8, 10, 12. Slides and article from EETimes. Video fra Xilinx: "FPGA Power Management HDL Coding Techniques".
11.03.2015	Espen Tallaksen and Alexander Wold	Perl	VHDL Testbench Design 1	Making good testbenches with Bitvis Utility Library; Lecture slides (www.bitvis.no).
17.03.2015	Roar Skogstr?m	Postscript	SystemVerilog 6	SystemVerilog for Verification chapter 8 and 10. Lecture slides are here.
18.03.2015	Roar Skogstr?m	Perl	VHDL Testbench Design 2	Command driven VHDL testbenches Lecture slides . P.J.Ashenden: The Designers Guide to VHDL; Chapter 17 (17.1-2). A complete example of a command driven testbench is here and with slides here. The example is NOT part of the curriculum.
25.03.2015	Roar Skogstr?m	Perl	SystemVerilog 7. Lab3 presentation.	SystemVerilog for Verification chapter 6. Lecture slides are here. Lab3 with submission deadline April 22'th 2015 is here.
08.04.2015	Alexander Wold	Perl	High Level Synthesis	Slides here
14.04.2015	Alexander Wold	Postscript	Partial Reconfiguration 1	Slides here
15.04.2015	Roar Skogstr?m	Perl	SystemVerilog 8. Lab4 presentation.	SystemVerilog for Verification chapter 9. Lecture slides are here. Lab4 with submission deadline May 20'th 2015 is here.
21.04.2015				AVLYST
22.04.2015	Roar Skogstr?m	Perl	SystemVerilog Universal Verification Methodology (UVM)	SystemVerilog UVM slides and MPEG4 files are here (304 MByte!)
19.05.2015	J?rgen Norendal, Alexander Wold og Roar Skogstr?m.	Postscript; kl.10:15-12.		Q&A

Published Jan. 9, 2015 6:14 PM - Last modified May 20, 2015 3:39 PM