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The last Q&A lecture will be on May 25'th 14:15-16.

Please send questions in advance by email!

Lab guidance for lab5 will be in the lab room on May 11'th and May 18'th from 14:00-19:00.

Examination guidance is posted her.

Lab5 with submission deadline May 19'th 2016 is here.

We will try to merge the two lessons:

Sequential circuit design,

Register Transfer Methodology Part I

and

Register Transfer Methodology Part II,

Clock domain crossings and handshake

on the Q&A lecture 4.4.2016. 

So please be prepared by watching the course videos in front of this lecture.

Lab4 with submission deadline April 18'th 2016 is here.

The new deadline is March 11th.

The answer of 22 * -14 is here.

Unfortunately Lab1 fails to run on the FPGA-board. This was a bit of a surprise, as it has been working fine in previous years. However, it is therefore sufficient that your solution is simulated correctly. You may deliver Lab1 on Friday 26.2.

Lab3 with submission deadline March 30'th 2016 is here.

Lab2 with submission deadline March 11'th 2016 is here.

Link here

Det er 2 ledige sommerjobber i FPGA utvikling ved Kongsberg Defence Communications i Asker. Se omtale av sommerjobbene here. Sommerjobbene vil bli omtalt i pausen p? forelesningen mandag 8.februar kl. 15:00-15.

Please check all available options on this doodle.

Lab1 with submission deadline February 17'th 2016 is here.

The lectures in Hardware Design on 1.2 and 8.2 have been swapped with the lectures in High Level Synthesis on 16.3 and 30.3.